In known semiconductor memory cells and methods for fabricating them, a material region of the memory cell, the material of which can adopt a plurality of phases which correspond to different values of a physical variable of the material of the material region of the memory cell and which are or can be assigned to different storage states of the semiconductor memory cell, is or has been provided as the storage element of the semiconductor memory cell, between a first electrode device and a second electrode device and in electrical contact with these electrode devices. The phase state of the storage element is programmed or erased in a suitable way, for example by corresponding heating, when writing and/or erasing the semiconductor memory cell with a phase change storage mechanism, and the storage state and the associated information content are read by determining the value of the physical variable and the corresponding association when reading the semiconductor memory cell.
A problem of known semiconductor memory cells having a phase change storage mechanism is that the electric currents for heating required to program or erase the states of the respective storage elements adopt relatively high levels which cannot readily be delivered by conventional semiconductor circuit arrangements on which they are based and which are customarily used in semiconductor memory devices. This is because firstly the programming or erasing of the respective states of the storage material of the storage elements is effected thermally by a corresponding flow of current through the storage material of the memory cell, and this flow of current is imparted by contact-connection with the first and second electrode devices. Since the geometric or physical extent of the storage material or of the material region of the memory cell has hitherto been limited by the lithographic resolution of the lithography technique used, the currents which are required for thermal programming or erasing do not drop below a defined level, and consequently the underlying circuit arrangements, which also have to realize the programming or erasing, have to be dimensioned accordingly in terms of their electrical power.
Therefore, the overall result is a restriction on the integration density both with regard to the geometric extent of the memory cell itself and with regard to the extent of the semiconductor circuit arrangement on which it is based and which has to realize the programming or erasing processes.
There is a need for a semiconductor memory having a high integration density of phase change memory cells, and a lower programming current.